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» Secure Memory Accesses on Networks-on-Chip
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OOPSLA
2010
Springer
14 years 8 months ago
Hera-JVM: a runtime system for heterogeneous multi-core architectures
Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores...
Ross McIlroy, Joe Sventek
CODES
2005
IEEE
14 years 11 months ago
FIDES: an advanced chip multiprocessor platform for secure next generation mobile terminals
We propose a secure platform on a chip multiprocessor, known as FIDES, in order to enable next generation mobile terminals to execute downloaded native applications for Linux. Its...
Hiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji ...
IPPS
2005
IEEE
15 years 3 months ago
Characterizing Secure Dynamic Web Applications Scalability
Security in the access to web contents and the interaction with web sites is becoming one of the most important issues in Internet. Servers need to provide certain levels of secur...
Jordi Guitart, Vicenç Beltran, David Carrer...
NOSSDAV
2010
Springer
15 years 2 months ago
RTP-miner: a real-time security framework for RTP fuzzing attacks
Real-time Transport Protocol (RTP) is a widely adopted standard for transmission of multimedia traffic in Internet telephony (commonly known as VoIP). Therefore, it is a hot poten...
M. Ali Akbar, Muddassar Farooq
CHES
2006
Springer
134views Cryptology» more  CHES 2006»
15 years 1 months ago
Read-Proof Hardware from Protective Coatings
In cryptography it is assumed that adversaries only have black box access to the secret keys of honest parties. In real life, however, the black box approach is not sufficient beca...
Pim Tuyls, Geert Jan Schrijen, Boris Skoric, Jan v...