Sciweavers

108 search results - page 17 / 22
» Security issues in high level architecture based distributed...
Sort
View
DAC
2007
ACM
15 years 10 months ago
Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
Ümit Y. Ogras, Diana Marculescu, Puru Choudha...
IEEEPACT
2009
IEEE
15 years 4 months ago
Quantifying the Potential of Program Analysis Peripherals
Abstract—As programmers are asked to manage more complicated parallel machines, it is likely that they will become increasingly dependent on tools such as multi-threaded data rac...
Mohit Tiwari, Shashidhar Mysore, Timothy Sherwood
HPCA
2009
IEEE
15 years 10 months ago
Accurate microarchitecture-level fault modeling for studying hardware faults
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...
Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu...
CNSR
2008
IEEE
140views Communications» more  CNSR 2008»
15 years 4 months ago
An Approach for Optimal Bandwidth Allocation in Packet Processing Systems
The increasing demand for more bandwidth and the increased application variety fuel the need for high performance network processors. A simple but highly repetitive task performed...
Mahmood Ahmadi, Stephan Wong
ADHOC
2008
132views more  ADHOC 2008»
14 years 9 months ago
Defending against cache consistency attacks in wireless ad hoc networks
Caching techniques can be used to reduce bandwidth consumption and data access delay in wireless ad hoc networks. When cache is used, the issue of cache consistency must be addres...
Wensheng Zhang, Guohong Cao