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» Selected failure mechanisms of modern power modules
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TELSYS
2002
126views more  TELSYS 2002»
14 years 11 months ago
Framework and Tool Support for Formal Verification of Highspeed Transfer Protocol Designs
Formal description techniques, verification methods, and their tool-based automated application meanwhile provide valuable support for the formal analysis of communication protocol...
Peter Herrmann, Heiko Krumm, Olaf Drögehorn, ...
87
Voted
ISPD
2006
ACM
68views Hardware» more  ISPD 2006»
15 years 5 months ago
Solving hard instances of floorplacement
Physical Design of modern systems on chip is extremely challenging. Such digital integrated circuits often contain tens of millions of logic gates, intellectual property blocks, e...
Aaron N. Ng, Igor L. Markov, Rajat Aggarwal, Venky...
101
Voted
ICS
2009
Tsinghua U.
15 years 4 months ago
Dynamic task set partitioning based on balancing memory requirements to reduce power consumption
ABSTRACT Because of technology advances power consumption has emerged up as an important design issue in modern high-performance microprocessors. As a consequence, research on redu...
Diana Bautista, Julio Sahuquillo, Houcine Hassan, ...
118
Voted
ECRTS
2010
IEEE
15 years 23 days ago
Partitioning Parallel Applications on Multiprocessor Reservations
A full exploitation of the computational power available in a multi-core platform requires the software to be specified in terms of parallel execution flows. At the same time, mode...
Giorgio C. Buttazzo, Enrico Bini, Yifan Wu
DAC
2008
ACM
16 years 20 days ago
TuneFPGA: post-silicon tuning of dual-Vdd FPGAs
Modern CMOS manufacturing processes have significant variability, which necessitates guard banding to achieve reasonable yield. We study an FPGA architecture with a dual voltage s...
Stephen Bijansky, Adnan Aziz