376 search results - page 50 / 76 » Self-Assembled Circuit Patterns |
94
Voted
ET
2000
14 years 11 months ago
2000
An efficient deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum num...
114
Voted
ENTCS
2011
14 years 6 months ago
2011
This paper presents a game semantics for a simply-typed λ-calculus with qbits constants and associated quantum operations. The resulting language is expressive enough to encode a...
ATS
2009
IEEE
15 years 6 months ago
2009
IEEE
SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compa...
ISMVL
2007
IEEE
15 years 6 months ago
2007
IEEE
The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a f...
DATE
2006
IEEE
15 years 5 months ago
2006
IEEE
— We present a probabilistic fault model that allows any number of gates in an integrated circuit to fail probabilistically. Tests for this fault model, determined using the theo...