605 search results - page 1 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
65
Voted
IFIP
1993
Springer
15 years 4 months ago
1993
Springer
An advanced Self-Timed Reduced Instruction Set Computer (ST-RISC) architecture is described. It is designed hierarchically, and is formally specified functionally at the various ...
107
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IEEEPACT
1998
IEEE
15 years 4 months ago
1998
IEEE
Conventional speculative architectures use branch prediction to evaluate the most likely execution path during program execution. However, certain branches are difficult to predic...
71
Voted
ASPDAC
2004
ACM
15 years 6 months ago
2004
ACM
71
Voted
ISSS
2002
IEEE
15 years 5 months ago
2002
IEEE
101
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DAC
2001
ACM
16 years 1 months ago
2001
ACM
New application-focused system-on-chip platforms motivate new application-specific processors. Configurable and extensible processor architectures offer the efficiency of tuned lo...