605 search results - page 107 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
ECTEL
2006
Springer
15 years 1 months ago
2006
Springer
In this paper, we present a proof of concept application of a technique that is designed explicitly for face to face collaboration software architectures. The objective is to minim...
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
As the last-level on-chip caches in chip-multiprocessors increase in size, the physical locality of on-chip data becomes important for delivering high performance. The non-uniform...
DAC
2010
ACM
15 years 1 months ago
2010
ACM
System optimization techniques based on dynamic voltage scaling (DVS) are widely used with the aim of reducing processor energy consumption. Inter-task DVS assigns the same voltag...
DAC
2004
ACM
15 years 10 months ago
2004
ACM
Current technology trends have led to the growing impact of both inter-die and intra-die process variations on circuit performance. While it is imperative to model parameter varia...
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...