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CAL
2002
14 years 9 months ago
MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research
Abstract-- Computer architects must determine how to most effectively use finite computational resources when running simulations to evaluate new architectural ideas. To facilitate...
A. J. KleinOsowski, David J. Lilja
CORR
2010
Springer
89views Education» more  CORR 2010»
14 years 10 months ago
Power optimized programmable embedded controller
Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functio...
M. Kamaraju, K. Lal Kishore, A. V. N. Tilak
IPPS
1996
IEEE
15 years 1 months ago
A Method for Register Allocation to Loops in Multiple Register File Architectures
Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocat...
David J. Kolson, Alexandru Nicolau, Nikil D. Dutt,...
ARITH
2001
IEEE
15 years 1 months ago
Computer Arithmetic-A Processor Architect's Perspective
The Instruction Set Architecture (ISA) of a programmable processor is the native languageof the machine. It defines the set of operations and resourcesthat are optimized for that ...
Ruby B. Lee
ISCC
2009
IEEE
210views Communications» more  ISCC 2009»
15 years 4 months ago
Towards a Java bytecodes compiler for Nios II soft-core processor
Reconfigurable computing is one of the most recent research topics in computer science. The Altera™ Nios II soft-core processor can be included in a large set of reconfigurable ...
Willian dos Santos Lima, Renata Spolon Lobato, Ale...