605 search results - page 38 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
KDD
2005
ACM
15 years 10 months ago
2005
ACM
Computer architects utilize simulation tools to evaluate the merits of a new design feature. The time needed to adequately evaluate the tradeoffs associated with adding any new fe...
VLSID
2004
IEEE
15 years 10 months ago
2004
IEEE
The design of any application on a configurable System-on-a-Chip (SoC) like Atmel's FPSLIC is subject to a lot of constraints stemming from requirements of the application an...
CASES
2005
ACM
14 years 11 months ago
2005
ACM
Instruction set customization accelerates the performance of applications by compressing the length of critical dependence paths and reducing the demands on processor resources. W...
JCIT
2007
14 years 9 months ago
2007
Queue computers are a viable option for embedded systems design. Queue computers feature a dense instruction set, high parallelism, low hardware complexity. In this paper we propo...
CP
2009
Springer
15 years 1 months ago
2009
Springer
Abstract. This paper considers the automatic generation of architectural tests (ATGP), a fundamental problem in processor validation. ATGPs are complex conditional constraint satis...