605 search results - page 42 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
PPOPP
2005
ACM
15 years 3 months ago
2005
ACM
Disk subsystem is known to be a major contributor to overall power consumption of high-end parallel systems. Past research proposed several architectural level techniques to reduc...
DSN
2002
IEEE
15 years 2 months ago
2002
IEEE
The architecture and implementation of the LEON-FT processor is presented. LEON-FT is a fault-tolerant 32-bit processor based on the SPARC V8 instruction set. The processors toler...
SIGCSE
2006
ACM
15 years 3 months ago
2006
ACM
We describe the implementation of “MARS,” a GUI, Java-based simulator for the MIPS assembly language. MIPS, the computer architecture underlying the simulated assembly languag...
CF
2005
ACM
14 years 11 months ago
2005
ACM
This paper evaluates how much extended dictionary-based code compression techniques can reduce the static code size. In their simplest form, such methods statically identify ident...
HPCA
2008
IEEE
15 years 10 months ago
2008
IEEE
Fetch gating mechanisms have been proposed to gate the processor pipeline to reduce the wasted energy consumption due to wrongpath (i.e. mis-speculated) instructions. These scheme...