605 search results - page 43 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
HPCA
2006
IEEE
15 years 10 months ago
2006
IEEE
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
ENTCS
2007
14 years 9 months ago
2007
We present a method for pipeline verification using SMT solvers. It is based on a non-deterministic “mother pipeline” machine (MOP) that abstracts the instruction set archite...
VEE
2012
ACM
13 years 5 months ago
2012
ACM
As cloud-based computation becomes increasingly important, providing a general computational interface to support datacenterscale programming has become an imperative research age...
ASPLOS
2000
ACM
15 years 2 months ago
2000
ACM
The emergence of the Internet as a trusted medium for commerce and communication has made cryptography an essential component of modern information systems. Cryptography provides ...
PPOPP
2010
ACM
15 years 7 months ago
2010
ACM
Loop vectorization, a key feature exploited to obtain high performance on Single Instruction Multiple Data (SIMD) vector architectures, is significantly hindered by irregular memo...