605 search results - page 45 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
WMPI
2004
ACM
15 years 3 months ago
2004
ACM
User-controllable coherence revives the idea of cooperation between software and hardware in an attempt to bridge the gap between efficient small-scale shared memory machines and m...
ET
2007
14 years 9 months ago
2007
In this paper, we focus on reliability, one of the most fundamental and important challenges, in the nanoelectronics environment. For a processor architecture based on the unreliab...
WMPI
2004
ACM
15 years 3 months ago
2004
ACM
Clustered microarchitectures are an effective organization to deal with the problem of wire delays and complexity by partitioning some of the processor resources. The organization ...
APCSAC
2001
IEEE
15 years 1 months ago
2001
IEEE
During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simula...
IEEEPACT
2003
IEEE
15 years 3 months ago
2003
IEEE
Graphics and media processing is quickly emerging to become one of the key computing workloads. Programmable graphics processors give designers extra flexibility by running a sma...