605 search results - page 47 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
ISLPED
2003
ACM
15 years 3 months ago
2003
ACM
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
CGO
2007
IEEE
15 years 1 months ago
2007
IEEE
Dynamic predication has been proposed to reduce the branch misprediction penalty due to hard-to-predict branch instructions. A recently proposed dynamic predication architecture, ...
SBACPAD
2007
IEEE
15 years 4 months ago
2007
IEEE
Code Compression has been used to alleviate the memory requirements as well as to improve performance and/or minimize energy consumption. On the other hand, implementing security ...
WMPI
2004
ACM
15 years 3 months ago
2004
ACM
Abstract. In this paper, we propose a processor architecture with programmable on-chip memory for a high-performance SMP (symmetric multi-processor) node named SCIMA-SMP (Software ...
IEEEPACT
2002
IEEE
15 years 2 months ago
2002
IEEE
In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel’s SSE and Motorola’s AltiVec that su...