605 search results - page 49 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
ARITH
2007
IEEE
15 years 4 months ago
2007
IEEE
The floating-point multiply-add fused (MAF) unit sets a new trend in the processor design to speed up floatingpoint performance in scientific and multimedia applications. This ...
ICMCS
2005
IEEE
15 years 3 months ago
2005
IEEE
In this research, an architecture that performs both forward and inverse lifting-based discrete wavelet transform is proposed. The proposed architecture reduces the hardware requi...
FPGA
2007
ACM
15 years 4 months ago
2007
ACM
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
HPCA
2008
IEEE
15 years 10 months ago
2008
IEEE
Hard-to-predict branches depending on longlatency cache-misses have been recognized as a major performance obstacle for modern microprocessors. With the widening speed gap between...
MICRO
1999
IEEE
15 years 2 months ago
1999
IEEE
Compressing the instructions of an embedded program is important for cost-sensitive low-power control-oriented embedded computing. A number of compression schemes have been propos...