605 search results - page 50 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
ECOOPW
1998
Springer
15 years 2 months ago
1998
Springer
Quality and economical aspects of software development are strictly related. Adaptability, as a feature of quality, fosters reuse and the resulting economies of scale. Domain anal...
IEEEPACT
2000
IEEE
15 years 2 months ago
2000
IEEE
Multimedia instruction set extensions have become a prominent feature in desktop microprocessor platforms, promising superior performance on a wide range of floating-point and int...
DAC
2003
ACM
15 years 10 months ago
2003
ACM
A binary decoder is a common component of software development tools such as instruction set simulators, disassemblers and debuggers. The efficiency of the decoder can have a sign...
DAC
2006
ACM
14 years 11 months ago
2006
ACM
Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving ...
ASAP
2009
IEEE
15 years 7 months ago
2009
IEEE
—The Cell processor consists of a general-purpose core and eight cores with a complete SIMD instruction set. Although originally designed for multimedia and gaming, it is current...