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ACMMSP
2004
ACM
125views Hardware» more  ACMMSP 2004»
15 years 3 months ago
Improving trace cache hit rates using the sliding window fill mechanism and fill select table
As superscalar processors become increasingly wide, it is inevitable that the large set of instructions to be fetched every cycle will span multiple noncontiguous basic blocks. Th...
Muhammad Shaaban, Edward Mulrane
ASPDAC
2005
ACM
102views Hardware» more  ASPDAC 2005»
14 years 11 months ago
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages
— Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design spa...
Oliver Schliebusch, Anupam Chattopadhyay, David Ka...
E2EMON
2006
IEEE
15 years 3 months ago
Active Probing Approach for Fault Localization in Computer Networks
—Active probing is an active network monitoring technique that has potential for developing effective solutions for fault localization. In this paper we use active probing to pre...
Maitreya Natu, Adarshpal S. Sethi
PDP
2011
IEEE
14 years 1 months ago
Quantifying Thread Vulnerability for Multicore Architectures
Abstract—Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, mu...
Isil Oz, Haluk Rahmi Topcuoglu, Mahmut T. Kandemir...
EVOW
2008
Springer
14 years 11 months ago
Architecture Performance Prediction Using Evolutionary Artificial Neural Networks
The design of computer architectures requires the setting of multiple parameters on which the final performance depends. The number of possible combinations make an extremely huge ...
Pedro A. Castillo, Antonio Miguel Mora, Juan Juli&...