605 search results - page 64 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
SC
2004
ACM
15 years 3 months ago
2004
ACM
This paper is structured as follows. Section 2 gives an architectural description of BlueGene/L. Section 3 analyzes the issue of “computational noise” – the effect that the o...
IPPS
1998
IEEE
15 years 2 months ago
1998
IEEE
In distributed-memory message-passing architectures reducing communication cost is extremely important. In this paper, we present a technique to optimize communication globally. O...
TVLSI
2008
14 years 9 months ago
2008
ion levels. The framework also supports the generation of test constraints, which can be satisfied using a constraint solver to generate tests. A compositional verification approac...
ASPLOS
2004
ACM
15 years 3 months ago
2004
ACM
We present a novel processor architecture designed specifically for use in low-power wireless sensor-network nodes. Our sensor network asynchronous processor (SNAP/LE) is based on...
EUROSYS
2011
ACM
14 years 1 months ago
2011
ACM
We present an effective technique for crosschecking an IEEE 754 floating-point program and its SIMD-vectorized version, implemented in KLEE-FP, an extension to the KLEE symbolic ...