605 search results - page 65 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
PASTE
2010
ACM
15 years 2 months ago
2010
ACM
Recently there has been significant interest in employing probabilistic techniques for fault localization. Using dynamic dependence information for multiple passing runs, learnin...
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PACT
2007
Springer
15 years 4 months ago
2007
Springer
Abstract. It has been already verified that hardware-supported finegrain synchronization provides a significant performance improvement over coarse-grained synchronization mecha...
HPCA
1996
IEEE
15 years 2 months ago
1996
IEEE
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
BIRTHDAY
2006
Springer
15 years 1 months ago
2006
Springer
We describe a gate level design of a FlexRay-like bus interface. An electronic control unit (ECU) is obtained by integrating this interface into the design of the verified VAMP pro...
DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
Smart cards are vulnerable to both invasive and non-invasive attacks. Specifically, non-invasive attacks using power and timing measurements to extract the cryptographic key has d...