605 search results - page 68 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
CGF
2006
14 years 10 months ago
2006
WPSD (Weighted Pose Space Deformation) is an example based skinning method for articulated body animation. The per-vertex computation required in WPSD can be parallelized in a SIM...
IPPS
2005
IEEE
15 years 3 months ago
2005
IEEE
— The DECOS architecture aims at combining the advantages of federated and integrated systems. The DECOS architecture divides the overall system into a set of nearly-independent ...
WMPI
2004
ACM
15 years 3 months ago
2004
ACM
During a program’s runtime, the stack and data segments of the main memory often contain much redundancy, which makes them good candidates for compression. Compression and decomp...
ICPP
1999
IEEE
15 years 2 months ago
1999
IEEE
Loops are the main time consuming part of programs based on floating point computations. The performance of the loops is limited either by recurrences in the computation or by the...
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DAC
2003
ACM
15 years 10 months ago
2003
ACM
The capability of performing architectural exploration has become essential for embedded microprocessor design in System-On-Chip. While many retargetable instruction set (ISA) sim...