Sciweavers

605 search results - page 73 / 121
» Self-Timed Architecture of a Reduced Instruction Set Compute...
Sort
View
IPPS
2010
IEEE
14 years 7 months ago
Scalable multi-pipeline architecture for high performance multi-pattern string matching
Multi-pattern string matching remains a major performance bottleneck in network intrusion detection and anti-virus systems for high-speed deep packet inspection (DPI). Although Aho...
Weirong Jiang, Yi-Hua Edward Yang, Viktor K. Prasa...
WWW
2004
ACM
15 years 10 months ago
Authoring of learning styles in adaptive hypermedia: problems and solutions
Learning styles, as well as the best ways of responding with corresponding instructional strategies, have been intensively studied in the classical educational (classroom) setting...
Natalia Stash, Alexandra I. Cristea, Paul De Bra
HPCA
2008
IEEE
15 years 10 months ago
Single-level integrity and confidentiality protection for distributed shared memory multiprocessors
Multiprocessor computer systems are currently widely used in commercial settings to run critical applications. These applications often operate on sensitive data such as customer ...
Brian Rogers, Chenyu Yan, Siddhartha Chhabra, Milo...
DAC
1995
ACM
15 years 1 months ago
Delayed Frontal Solution for Finite-Element Based Resistance Extraction
To save memory, layout-to-circuit extractors that use the Finite-Element Method for resistance extraction usually solve the corresponding set of equations with a frontal solution ...
N. P. van der Meijs, Arjan J. van Genderen
FCCM
2003
IEEE
113views VLSI» more  FCCM 2003»
15 years 3 months ago
Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development
Although domain-specialized FPGAs can offer significant area, speed and power improvements over conventional reconfigurable devices, there are several unique and unexplored design...
Kenneth Eguro, Scott Hauck