605 search results - page 75 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
HPCA
2001
IEEE
15 years 10 months ago
2001
IEEE
Value prediction is a relatively new technique to increase the Instruction Level Parallelism (ILP) in future microprocessors. An important problem when designing a value predictor...
HPCA
2005
IEEE
15 years 10 months ago
2005
IEEE
Due to increasing power densities, both on-chip average and peak temperatures are fast becoming a serious bottleneck in processor design. This is due to the cost of removing the h...
ISHPC
2000
Springer
15 years 1 months ago
2000
Springer
Deeply pipelined high performance processors require highly accurate branch prediction to drive their instruction fetch. However there remains a class of events which are not easi...
LCPC
2000
Springer
15 years 1 months ago
2000
Springer
This paper presents recursion unrolling, a technique for improving the performance of recursive computations. Conceptually, recursion unrolling inlines recursive calls to reduce c...
SBACPAD
2005
IEEE
15 years 3 months ago
2005
IEEE
The time required to simulate a complete benchmark program using the cycle-accurate model of a microprocessor can be prohibitively high. One of the proposed methodologies, represe...