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SPIN
2004
Springer
15 years 11 months ago
Validation of UML Models via a Mapping to Communicating Extended Timed Automata
Abstract. We present a technique and a tool for model-checking operational UML models based on a mapping of object oriented UML models into a framework of communicating extended ti...
Iulian Ober, Susanne Graf, Ileana Ober
FORMATS
2003
Springer
15 years 11 months ago
Performance Analysis of Probabilistic Timed Automata Using Digital Clocks
Probabilistic timed automata, a variant of timed automata extended with discrete probability distributions, is a specification formalism suitable for describing both nondeterminis...
Marta Z. Kwiatkowska, Gethin Norman, David Parker,...
FORMATS
2007
Springer
15 years 10 months ago
Partial Order Reduction for Verification of Real-Time Components
Abstract. We describe a partial order reduction technique for a realtime component model. Components are described as timed automata with data ports, which can be composed in stati...
John Håkansson, Paul Pettersson
FORMATS
2006
Springer
15 years 9 months ago
Temporal Logic Verification Using Simulation
In this paper, we consider a novel approach to the temporal logic verification problem of continuous dynamical systems. Our methodology has the distinctive feature that enables the...
Georgios E. Fainekos, Antoine Girard, George J. Pa...
FORMATS
2006
Springer
15 years 9 months ago
Integrating Discrete- and Continuous-Time Metric Temporal Logics Through Sampling
Abstract. Real-time systems usually encompass parts that are best described by a continuous-time model, such as physical processes under control, together with other components tha...
Carlo A. Furia, Matteo Rossi