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ASPDAC
2009
ACM
184views Hardware» more  ASPDAC 2009»
15 years 1 months ago
FastRoute 4.0: global router with efficient via minimization
The number of vias generated during the global routing stage is a critical factor for the yield of final circuits. However, most global routers only approach the problem by chargin...
Yue Xu, Yanheng Zhang, Chris Chu
IJFCS
2006
58views more  IJFCS 2006»
14 years 9 months ago
Covering of Transient Simulation of Feedback-free Circuits by Binary Analysis
Transient simulation of a gate circuit is an efficient method of counting signal changes occurring during a transition of the circuit. It is known that this simulation covers the ...
Yuli Ye, Janusz A. Brzozowski
GECCO
2006
Springer
143views Optimization» more  GECCO 2006»
15 years 1 months ago
A hybridized genetic parallel programming based logic circuit synthesizer
Genetic Parallel Programming (GPP) is a novel Genetic Programming paradigm. Based on the GPP paradigm and a local search operator - FlowMap, a logic circuit synthesizing system in...
Wai Shing Lau, Kin-Hong Lee, Kwong-Sak Leung
ICCAD
2007
IEEE
124views Hardware» more  ICCAD 2007»
15 years 6 months ago
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits
Abstract— Thermal issues are a primary concern in the threedimensional (3D) integrated circuit (IC) design. Temperature, area, and wire length must be simultaneously optimized du...
Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. ...
IACR
2011
128views more  IACR 2011»
13 years 9 months ago
Sign Modules in Secure Arithmetic Circuits
In this paper, we study the complexity of secure multiparty computation using only the secure arithmetic black-box of a finite field, counting the cost by the number of secure m...
Ching-Hua Yu