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DEON
2006
Springer
15 years 3 months ago
Counts-as: Classification or Constitution? An Answer Using Modal Logic
Abstract. By making use of modal logic techniques, the paper disentangles two semantically different readings of statements of the type X counts as Y in context C (the classificato...
Davide Grossi, John-Jules Ch. Meyer, Frank Dignum
ACSD
2007
IEEE
103views Hardware» more  ACSD 2007»
15 years 6 months ago
Output-Determinacy and Asynchronous Circuit Synthesis
Signal Transition Graphs (STG) are a formalism for the description of asynchronous circuit behaviour. In this paper we propose (and justify) a formal semantics of nondeterministic...
Victor Khomenko, Mark Schäfer, Walter Vogler
DAC
2005
ACM
16 years 22 days ago
Logic block clustering of large designs for channel-width constrained FPGAs
In this paper we present a system level technique for mapping large, multiple-IP-block designs to channel-width constrained FPGAs. Most FPGA clustering tools [2, 3, 11] aim to red...
Marvin Tom, Guy G. Lemieux
ITC
1999
IEEE
105views Hardware» more  ITC 1999»
15 years 4 months ago
Finite state machine synthesis with concurrent error detection
A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are...
Chaohuang Zeng, Nirmal R. Saxena, Edward J. McClus...
ERSA
2006
70views Hardware» more  ERSA 2006»
15 years 1 months ago
Differential Reconfiguration Architecture suitable for a Holographic Memory
Optically Reconfigurable Gate Arrays (ORGAs), by exploiting the large storage capacity of holographic memory, offer the possibility of providing a virtual gate count that is much l...
Minoru Watanabe, Mototsugu Miyano, Fuminori Kobaya...