233 search results - page 24 / 47 » Semantical Counting Circuits |
ICCD
2006
IEEE
15 years 8 months ago
2006
IEEE
—X-filling is preferred for low-capture-power scan test generation, since it reduces IR-drop-induced yield loss without the need of any circuit modification. However, the effecti...
ICCAD
2007
IEEE
15 years 8 months ago
2007
IEEE
An algorithm for technology mapping of combinational and sequential logic networks is proposed and applied to mapping into K-input lookup-tables (K-LUTs). The new algorithm avoids...
100
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FMCAD
2007
Springer
15 years 6 months ago
2007
Springer
We present a formulation of retiming to minimize the number of registers in a design by iterating a maximum network flow problem. The retiming returned will be the optimum one whi...
ICCAD
1999
IEEE
15 years 4 months ago
1999
IEEE
In this paper, we present a new approach to the problem of inverter elimination in domino logic synthesis. A small piece of static CMOS logic is introduced to the circuit to avoid...
100
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ISMVL
1998
IEEE
15 years 4 months ago
1998
IEEE
The use of Look-Up Tables (LUTs) is extended from binary to multiple-valued logic (MVL) circuits. A multiplevalued LUT can be implemented using both current-mode and voltage-mode ...