Sciweavers

115 search results - page 2 / 23
» Sequential Circuit Verification Using Symbolic Model Checkin...
Sort
View
ASPDAC
2001
ACM
126views Hardware» more  ASPDAC 2001»
13 years 10 months ago
A new partitioning scheme for improvement of image computation
Abstract-- Image computation is the core operation for optimization and formal verification of sequential systems like controllers or protocols. State exploration techniques based ...
Christoph Meinel, Christian Stangier
CAV
1990
Springer
114views Hardware» more  CAV 1990»
13 years 10 months ago
Formal Verification of Digital Circuits Using Symbolic Ternary System Models
Ternary system modeling involves extending the traditional set of binary values
Randal E. Bryant, Carl-Johan H. Seger
CAV
2003
Springer
153views Hardware» more  CAV 2003»
13 years 11 months ago
Interpolation and SAT-Based Model Checking
Abstract. We consider a fully SAT-based method of unbounded symbolic model checking based on computing Craig interpolants. In benchmark studies using a set of large industrial circ...
Kenneth L. McMillan
ENTCS
2006
112views more  ENTCS 2006»
13 years 6 months ago
Distributed Symbolic Bounded Property Checking
In this paper we describe an algorithm for distributed, BDD-based bounded property checking and its implementation in the verification tool SymC. The distributed algorithm verifie...
Pradeep Kumar Nalla, Roland J. Weiss, Prakash Moha...
ISSTA
2006
ACM
14 years 9 days ago
Using model checking with symbolic execution to verify parallel numerical programs
We present a method to verify the correctness of parallel programs that perform complex numerical computations, including computations involving floating-point arithmetic. The me...
Stephen F. Siegel, Anastasia Mironova, George S. A...