Abstract— Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that significa...
In this paper a three-parameter bifurcation analysis of a piecewise-affine map is carried out. Such a map derives from a well-known map which has good features from its circuit im...
Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. Howev...
Partial Scan techniques have been widely accepted as an effective solution to improve sequential ATPG performance while keeping acceptable area and performance overheads. Several ...
Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda,...
| This paper reports the design of BIST structures for sequential machines. Testability of an FSM is limited due to the fact that some machine states remain unreachable and some ac...
Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, D...