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» Sequential Circuits for Relational Analysis
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ASPDAC
2000
ACM
95views Hardware» more  ASPDAC 2000»
15 years 3 months ago
FSM decomposition by direct circuit manipulation applied to low power design
Abstract— Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that significa...
José C. Monteiro, Arlindo L. Oliveira
IJBC
2006
49views more  IJBC 2006»
14 years 11 months ago
Bifurcation Analysis of a Circuit-Related Generalization of the Shipmap
In this paper a three-parameter bifurcation analysis of a piecewise-affine map is carried out. Such a map derives from a well-known map which has good features from its circuit im...
Federico Bizzarri, Marco Storace, Laura Gardini
ASYNC
2007
IEEE
132views Hardware» more  ASYNC 2007»
15 years 5 months ago
Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis
Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. Howev...
Tiberiu Chelcea, Girish Venkataramani, Seth Copen ...
DATE
1998
IEEE
82views Hardware» more  DATE 1998»
15 years 3 months ago
Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection
Partial Scan techniques have been widely accepted as an effective solution to improve sequential ATPG performance while keeping acceptable area and performance overheads. Several ...
Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda,...
VLSID
2002
IEEE
142views VLSI» more  VLSID 2002»
15 years 11 months ago
Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area
| This paper reports the design of BIST structures for sequential machines. Testability of an FSM is limited due to the fact that some machine states remain unreachable and some ac...
Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, D...