302 search results - page 42 / 61 » Sequential circuits for program analysis |
97
Voted
CC
2010
Springer
15 years 5 months ago
2010
Springer
On Chip Multiprocessors (CMP), it is common that multiple cores share certain levels of cache. The sharing increases the contention in cache and memory-to-chip bandwidth, further h...
108
Voted
PPOPP
2003
ACM
15 years 3 months ago
2003
ACM
Speculative multithreading (SpMT) architecture can exploit thread-level parallelism that cannot be identified statically. Speedup can be obtained by speculatively executing threa...
MICRO
2002
IEEE
15 years 3 months ago
2002
IEEE
To find the best designs, architects must rapidly simulate many design alternatives and have confidence in the results. Unfortunately, the most prevalent simulator construction ...
TOCS
2012
13 years 21 days ago
2012
We analyze the I/O behavior of iBench, a new collection of productivity and multimedia application workloads. Our analysis reveals a number of differences between iBench and typic...
102
Voted
ICCAD
2007
IEEE
15 years 2 months ago
2007
IEEE
Stepwise refinement is at the core of many approaches to synthesis and optimization of hardware and software systems. For instance, it can be used to build a synthesis approach for...