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TCAD
2011
14 years 4 months ago
Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs
—Pre-bond testing of 3-D stacked integrated circuits (ICs) involves testing each individual die before bonding. The overall yield of 3-D ICs improves with pre-bond testability be...
Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung K...
IPPS
2008
IEEE
15 years 4 months ago
SNAP, Small-world Network Analysis and Partitioning: An open-source parallel graph framework for the exploration of large-scale
We present SNAP (Small-world Network Analysis and Partitioning), an open-source graph framework for exploratory study and partitioning of large-scale networks. To illustrate the c...
David A. Bader, Kamesh Madduri
ECCV
2002
Springer
15 years 11 months ago
An Affine Invariant Interest Point Detector
This paper presents a novel approach for detecting affine invariant interest points. Our method can deal with significant affine transformations including large scale changes. Such...
Krystian Mikolajczyk, Cordelia Schmid
ISPD
2003
ACM
133views Hardware» more  ISPD 2003»
15 years 2 months ago
Closed form expressions for extending step delay and slew metrics to ramp inputs
: Recent years have seen significant research in finding closed form expressions for the delay of an RC circuit that improves upon the Elmore delay model. However, several of these...
Chandramouli V. Kashyap, Charles J. Alpert, Frank ...
ICCAD
2009
IEEE
118views Hardware» more  ICCAD 2009»
14 years 7 months ago
Pre-bond testable low-power clock tree design for 3D stacked ICs
Pre-bond testing of 3D stacked ICs involves testing individual dies before bonding. The overall yield of 3D ICs improves with prebond testability because designers can avoid stack...
Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung K...