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» Set functions for functional logic programming
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ISPD
1999
ACM
98views Hardware» more  ISPD 1999»
15 years 2 months ago
Towards synthetic benchmark circuits for evaluating timing-driven CAD tools
For the development and evaluation of CAD-tools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable cha...
Dirk Stroobandt, Peter Verplaetse, Jan Van Campenh...
HUC
1999
Springer
15 years 2 months ago
Advanced Interaction in Context
Mobile information appliances are increasingly used in numerous different situations and locations, setting new requirements to their interaction methods. When the user's situ...
Albrecht Schmidt, Kofi Asante Aidoo, Antti Takaluo...
DAC
1994
ACM
15 years 1 months ago
Automatic Verification of Pipelined Microprocessors
Abstract - We address the problem of automatically verifying large digital designs at the logic level, against high-level specifications. In this paper, we present a methodology wh...
Vishal Bhagwati, Srinivas Devadas
CIKM
2006
Springer
15 years 1 months ago
SaLSa: computing the skyline without scanning the whole sky
Skyline queries compute the set of Pareto-optimal tuples in a relation, i.e., those tuples that are not dominated by any other tuple in the same relation. Although several algorit...
Ilaria Bartolini, Paolo Ciaccia, Marco Patella
FPGA
2006
ACM
129views FPGA» more  FPGA 2006»
15 years 1 months ago
Power-aware RAM mapping for FPGA embedded memory blocks
Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a ...
Russell Tessier, Vaughn Betz, David Neto, Thiagara...