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IPPS
2010
IEEE
14 years 9 months ago
A PRAM-NUMA model of computation for addressing low-TLP workloads
It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy par...
Martti Forsell
EUROPAR
1998
Springer
15 years 3 months ago
Analysing an SQL Application with a BSPlib Call-Graph Profiling Tool
This paper illustrates the use of a post-mortem call-graph profiling tool in the analysis of an SQL query processing application written using BSPIib [4]. Unlike other parallel pro...
Jonathan M. D. Hill, Stephen A. Jarvis, Constantin...
SIGMETRICS
2010
ACM
201views Hardware» more  SIGMETRICS 2010»
15 years 4 months ago
Transparent, lightweight application execution replay on commodity multiprocessor operating systems
We present S, the first system to provide transparent, lowoverhead application record-replay and the ability to go live from replayed execution. S i...
Oren Laadan, Nicolas Viennot, Jason Nieh
ASPLOS
2008
ACM
15 years 1 months ago
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-...
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IEEEPACT
2008
IEEE
15 years 6 months ago
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor
Moore’s Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneo...
Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aa...