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» Short circuit power consumption of glitches
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ICCD
2005
IEEE
116views Hardware» more  ICCD 2005»
15 years 6 months ago
Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis
Consideration of pairs of transition in probabilistic simulation allows power estimation for digital circuits in which inertial delays can filter glitches [5]. However, the merit ...
Fei Hu, Vishwani D. Agrawal
GLVLSI
1998
IEEE
119views VLSI» more  GLVLSI 1998»
15 years 1 months ago
Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines
The dynamic and short-circuit power consumption of a complementary metal
Yehea I. Ismail, Eby G. Friedman, José Luis...
ISLPED
1995
ACM
193views Hardware» more  ISLPED 1995»
15 years 1 months ago
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
We consider the problem of transistor sizing in a static CMOS layout to minimizethe power consumption of the circuit subject to a given delay constraint. Based on our characteriza...
Manjit Borah, Robert Michael Owens, Mary Jane Irwi...
ICCAD
2006
IEEE
117views Hardware» more  ICCAD 2006»
15 years 3 months ago
A timing dependent power estimation framework considering coupling
In this paper, we propose a timing dependent dynamic power estimation framework that considers the impact of coupling and glitches. We show that relative switching activities and ...
Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, H...
VLSID
2003
IEEE
103views VLSI» more  VLSID 2003»
15 years 9 months ago
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...