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» Short circuit power consumption of glitches
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ISLPED
1995
ACM
129views Hardware» more  ISLPED 1995»
15 years 1 months ago
CMOS dynamic power estimation based on collapsible current source transistor modeling
When estimating the dynamic power dissipated by a circuit di erent methods ranging from numeric analog simulation to event-driven logic simulation have been proposed. However, as ...
Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Pet...
ASPDAC
2007
ACM
117views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Short-Circuit Compiler Transformation: Optimizing Conditional Blocks
Abstract-- We present the short-circuit code transformation technique, intended for embedded compilers. The transformation technique optimizes conditional blocks in high-level prog...
Mohammad Ali Ghodrat, Tony Givargis, Alex Nicolau
ISLPED
1995
ACM
134views Hardware» more  ISLPED 1995»
15 years 1 months ago
High-throughput and low-power DSP using clocked-CMOS circuitry
We argue that the clocked-CMOS (C2MOS) circuit family provides a very high throughput and low power alternative to other existing circuit techniques for the fast developing market...
Manjit Borah, Robert Michael Owens, Mary Jane Irwi...
ISLPED
2007
ACM
138views Hardware» more  ISLPED 2007»
14 years 11 months ago
Power optimal MTCMOS repeater insertion for global buses
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors ...
Hanif Fatemi, Behnam Amelifard, Massoud Pedram
VLSID
2005
IEEE
139views VLSI» more  VLSID 2005»
15 years 9 months ago
Variable Input Delay CMOS Logic for Low Power Design
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...