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90
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HPCA
2005
IEEE
16 years 2 months ago
A Unified Compressed Memory Hierarchy
The memory system's large and growing contribution to system performance motivates more aggressive approaches to improving its efficiency. We propose and analyze a memory hie...
Erik G. Hallnor, Steven K. Reinhardt
ICCAD
2007
IEEE
123views Hardware» more  ICCAD 2007»
15 years 10 months ago
Mapping model with inter-array memory sharing for multidimensional signal processing
Abstract – The storage requirements in data-intensive signal processing systems (including applications in video and image processing, artificial vision, medical imaging, real-t...
Ilie I. Luican, Hongwei Zhu, Florin Balasa
115
Voted
FCCM
2007
IEEE
108views VLSI» more  FCCM 2007»
15 years 8 months ago
Configurable Transactional Memory
Programming efficiency of heterogeneous concurrent systems is limited by the use of lock-based synchronization mechanisms. Transactional memories can greatly improve the programmi...
Christoforos Kachris, Chidamber Kulkarni
102
Voted
CONCURRENCY
2006
140views more  CONCURRENCY 2006»
15 years 1 months ago
An efficient memory operations optimization technique for vector loops on Itanium 2 processors
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
William Jalby, Christophe Lemuet, Sid Ahmed Ali To...
217
Voted
ASPLOS
2011
ACM
14 years 5 months ago
DoublePlay: parallelizing sequential logging and replay
Deterministic replay systems record and reproduce the execution of a hardware or software system. In contrast to replaying execution on uniprocessors, deterministic replay on mult...
Kaushik Veeraraghavan, Dongyoon Lee, Benjamin West...