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IPPS
2003
IEEE
15 years 9 months ago
So Many States, So Little Time: Verifying Memory Coherence in the Cray X1
This paper investigates a complexity-effective technique for verifying a highly distributed directory-based cache coherence protocol. We develop a novel approach called “witnes...
Dennis Abts, Steve Scott, David J. Lilja
EUROPAR
2003
Springer
15 years 9 months ago
Dynamic Load Balancing for I/O- and Memory-Intensive Workload in clusters Using a Feedback Control Mechanism
1 One common assumption of the existing models of load balancing is that the weights of resources and I/O buffer size are statically configured. Though the static configuration ...
Xiao Qin, Hong Jiang, Yifeng Zhu, David R. Swanson
HPCA
1999
IEEE
15 years 8 months ago
Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors
Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not e...
Murthy Durbhakula, Vijay S. Pai, Sarita V. Adve
DAC
1997
ACM
15 years 8 months ago
Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets
The paper presents an algorithm to determine the close-tosmallest possible data buffer sizes for arbitrary synchronous data flow (SDF) applications, such that we can guarantee the...
Marleen Adé, Rudy Lauwereins, J. A. Peperst...
APLAS
2008
ACM
15 years 6 months ago
Certified Reasoning in Memory Hierarchies
Abstract. Parallel programming is rapidly gaining importance as a vector to develop high performance applications that exploit the improved capabilities of modern computer architec...
Gilles Barthe, César Kunz, Jorge Luis Sacch...