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STORAGESS
2005
ACM
15 years 10 months ago
An electric fence for kernel buffers
Improper access of data buffers is one of the most common errors in programs written in assembler, C, C++, and several other languages. Existing programs and OSs frequently acces...
Nikolai Joukov, Aditya Kashyap, Gopalan Sivathanu,...
3DIC
2009
IEEE
184views Hardware» more  3DIC 2009»
15 years 11 months ago
Architectural evaluation of 3D stacked RRAM caches
The first memristor, originally theorized by Dr. Leon Chua in 1971, was identified by a team at HP Labs in 2008. This new fundamental circuit element is unique in that its resis...
Dean L. Lewis, HsienHsin S. Lee
RTSS
2009
IEEE
15 years 11 months ago
Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores
—Memory accesses form an important source of timing unpredictability. Timing analysis of real-time embedded software thus requires bounding the time for memory accesses. Multipro...
Yan Li, Vivy Suhendra, Yun Liang, Tulika Mitra, Ab...
CAL
2007
15 years 4 months ago
Chameleon: A High Performance Flash/FRAM Hybrid Solid State Disk Architecture
—Flash memory solid state disk (SSD) is gaining popularity and replacing hard disk drive (HDD) in mobile computing systems such as ultra mobile PCs (UMPCs) and notebook PCs becau...
Jinhyuk Yoon, Eyee Hyun Nam, Yoon Jae Seong, Hongs...
TJS
2008
95views more  TJS 2008»
15 years 4 months ago
Combating I-O bottleneck using prefetching: model, algorithms, and ramifications
Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter [?]. More than a decade of architectural a...
Akshat Verma, Sandeep Sen