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ISPASS
2005
IEEE
15 years 10 months ago
Balancing Performance and Reliability in the Memory Hierarchy
Cosmic-ray induced soft errors in cache memories are becoming a major threat to the reliability of microprocessor-based systems. In this paper, we present a new method to accurate...
Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Ta...
NLDB
2001
Springer
15 years 9 months ago
"Where Are the Christmas Decorations?": A Memory Assistant for Storage Locations
At Hewlett-Packard Laboratories we want to know how inexpensive it can be to endow mobile personal assistants with the ability to speak naturally with their users. To this end, we ...
Lewis G. Creary, Michael VanHilst
DATE
2000
IEEE
140views Hardware» more  DATE 2000»
15 years 9 months ago
Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from C
-- One of the greatest challenges in C/C++-based design methodology is to efficiently map C/C++ models into hardware. Many of the networking and multimedia applications implemente...
Luc Séméria, Koichi Sato, Giovanni D...
129
Voted
ICS
1999
Tsinghua U.
15 years 8 months ago
Improving memory hierarchy performance for irregular applications
The performance of irregular applications on modern computer systems is hurt by the wide gap between CPU and memory speeds because these applications typically underutilize multi-...
John M. Mellor-Crummey, David B. Whalley, Ken Kenn...
ISCA
1993
IEEE
137views Hardware» more  ISCA 1993»
15 years 8 months ago
Transactional Memory: Architectural Support for Lock-Free Data Structures
A shared data structure is lock-free if its operations do not require mutual exclusion. If one process is interrupted in the middle of an operation, other processes will not be pr...
Maurice Herlihy, J. Eliot B. Moss