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127
Voted
HPCA
2001
IEEE
16 years 4 months ago
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
DSN
2009
IEEE
15 years 11 months ago
Fast memory state synchronization for virtualization-based fault tolerance
Virtualization provides the possibility of whole machine migration and thus enables a new form of fault tolerance that is completely transparent to applications and operating syst...
Maohua Lu, Tzi-cker Chiueh
121
Voted
DSN
2007
IEEE
15 years 11 months ago
Protecting Cryptographic Keys from Memory Disclosure Attacks
Cryptography has become an indispensable mechanism for securing systems, communications and applications. While offering strong protection, cryptography makes the assumption that ...
Keith Harrison, Shouhuai Xu
ISCA
2005
IEEE
101views Hardware» more  ISCA 2005»
15 years 10 months ago
Virtualizing Transactional Memory
Writing concurrent programs is difficult because of the complexity of ensuring proper synchronization. Conventional lock-based synchronization suffers from wellknown limitations, ...
Ravi Rajwar, Maurice Herlihy, Konrad K. Lai
FASE
2005
Springer
15 years 10 months ago
Checking Memory Safety with Blast
Abstract. Blast is an automatic verification tool for checking temporal safety properties of C programs. Given a C program and a temporal safety property, Blast statically proves ...
Dirk Beyer, Thomas A. Henzinger, Ranjit Jhala, Rup...