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ISCA
2007
IEEE
162views Hardware» more  ISCA 2007»
15 years 11 months ago
BulkSC: bulk enforcement of sequential consistency
While Sequential Consistency (SC) is the most intuitive memory consistency model and the one most programmers likely assume, current multiprocessors do not support it. Instead, th...
Luis Ceze, James Tuck, Pablo Montesinos, Josep Tor...
MICRO
2007
IEEE
188views Hardware» more  MICRO 2007»
15 years 11 months ago
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses...
Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Fal...
DATE
2005
IEEE
104views Hardware» more  DATE 2005»
15 years 10 months ago
Queue Management in Network Processors
: - One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at...
Ioannis Papaefstathiou, Theofanis Orphanoudakis, G...
132
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ISCA
2005
IEEE
121views Hardware» more  ISCA 2005»
15 years 10 months ago
Direct Cache Access for High Bandwidth Network I/O
Recent I/O technologies such as PCI-Express and 10Gb Ethernet enable unprecedented levels of I/O bandwidths in mainstream platforms. However, in traditional architectures, memory ...
Ram Huggahalli, Ravi R. Iyer, Scott Tetrick
PDCAT
2004
Springer
15 years 10 months ago
View-Oriented Parallel Programming and View-Based Consistency
Abstract. This paper proposes a novel View-Oriented Parallel Programming style for parallel programming on cluster computers. ViewOriented Parallel Programming is based on Distribu...
Zhiyi Huang, Martin K. Purvis, Paul Werstein