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SAC
2006
ACM
15 years 11 months ago
Building the functional performance model of a processor
In this paper, we present an efficient procedure for building a piecewise linear function approximation of the speed function of a processor with hierarchical memory structure. Th...
Alexey L. Lastovetsky, Ravi Reddy, Robert Higgins
EUROPAR
1997
Springer
15 years 9 months ago
Prefetching and Multithreading Performance in Bus-Based Multiprocessors with Petri Nets
The large latency of memory accesses is a major obstacle in obtaining high processor utilization in large scale shared-memory multiprocessors. Access to remote memory is likely to ...
Edward D. Moreno, Sergio Takeo Kofuji, Marcelo H. ...
DSN
2004
IEEE
15 years 8 months ago
An Architectural Framework for Providing Reliability and Security Support
This paper explores hardware-implemented error-detection and security mechanisms embedded as modules in a hardware-level framework called the Reliability and Security Engine (RSE)...
Nithin Nakka, Zbigniew Kalbarczyk, Ravishankar K. ...
CIDR
2009
98views Algorithms» more  CIDR 2009»
15 years 6 months ago
From Declarative Languages to Declarative Processing in Computer Games
Recent work has shown that we can dramatically improve the performance of computer games and simulations through declarative processing: Character AI can be written in an imperati...
Ben Sowell, Alan J. Demers, Johannes Gehrke, Nitin...
133
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SSS
2010
Springer
15 years 3 months ago
"Slow Is Fast" for Wireless Sensor Networks in the Presence of Message Losses
Abstract. Transformations from shared memory model to wireless sensor networks (WSNs) quickly become inefficient in the presence of prevalent message losses in WSNs, and this prohi...
Mahesh Arumugam, Murat Demirbas, Sandeep S. Kulkar...