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CDES
2006
89views Hardware» more  CDES 2006»
14 years 11 months ago
Autonomous Instruction Memory Equipped with Dynamic Branch Handling Capability
Memory accesses have always been a speed-limiting factor, and memory bandwidth has always been an intensively contended scarce resource. Nevertheless, with recent pervasive emergen...
Hui-Chin Yang, Chung-Ping Chung
CAL
2006
14 years 9 months ago
A Page-based Hybrid (Software-Hardware) Dynamic Memory Allocator
Modern programming languages often include complex mechanisms for dynamic memory allocation and garbage collection. These features drive the need for more efficient implementation ...
Wentong Li, Saraju P. Mohanty, Krishna M. Kavi
ACNS
2011
Springer
231views Cryptology» more  ACNS 2011»
14 years 1 months ago
Cold Boot Key Recovery by Solving Polynomial Systems with Noise
A method for extracting cryptographic key material from DRAM used in modern computers has been recently proposed in [9]; the technique was called Cold Boot attacks. When considerin...
Martin Albrecht, Carlos Cid
VLSID
2001
IEEE
118views VLSI» more  VLSID 2001»
15 years 10 months ago
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language
Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizationsfor programmable systems assumed a fixed cache hierarchy. Withthe wideningproce...
Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexand...
HICSS
1995
IEEE
109views Biometrics» more  HICSS 1995»
15 years 1 months ago
The architecture of an optimistic CPU: the WarpEngine
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
John G. Cleary, Murray Pearson, Husam Kinawi