4747 search results - page 387 / 950 » Shuffle Memory System |
182
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TC
2008
15 years 6 months ago
2008
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
156
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TCAD
2008
15 years 6 months ago
2008
New fusion memory devices consisting of multiple heterogeneous memory components in a single die or package offer efficient ways to optimize embedded systems in terms of energy, pe...
149
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SYSTOR
2010
ACM
15 years 11 months ago
2010
ACM
I/O intensive workloads running in virtual machines can suffer massive performance degradation. Direct assignment of I/O devices to virtual machines is the best performing I/O vir...
217
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SIGMETRICS
1996
ACM
15 years 10 months ago
1996
ACM
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simul...
147
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HPCA
2005
IEEE
16 years 6 months ago
2005
IEEE
Many important applications exhibit large amounts of data parallelism, and modern computer systems are designed to take advantage of it. While much of the computation in the multi...