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ISCA
2010
IEEE
170views Hardware» more  ISCA 2010»
15 years 6 months ago
Relax: an architectural framework for software recovery of hardware faults
As technology scales ever further, device unreliability is creating excessive complexity for hardware to maintain the illusion of perfect operation. In this paper, we consider whe...
Marc de Kruijf, Shuou Nomura, Karthikeyan Sankaral...
ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
15 years 6 months ago
A case for FAME: FPGA architecture model execution
Given the multicore microprocessor revolution, we argue that the architecture research community needs a dramatic increase in simulation capacity. We believe FPGA Architecture Mod...
Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bi...
SPAA
2010
ACM
15 years 6 months ago
TLRW: return of the read-write lock
TL2 and similar STM algorithms deliver high scalability based on write-locking and invisible readers. In fact, no modern STM design locks to read along its common execution path b...
David Dice, Nir Shavit
EUROPAR
2009
Springer
15 years 6 months ago
SSD-HDD-Hybrid Virtual Disk in Consolidated Environments
Abstract. With the prevalence of multi-core processors and cloud computing, the server consolidation using virtualization has increasingly expanded its territory, and the degree of...
Heeseung Jo, Youngjin Kwon, Hwanju Kim, Euiseong S...
DATE
1998
IEEE
153views Hardware» more  DATE 1998»
15 years 5 months ago
An Energy-Conscious Exploration Methodology for Reconfigurable DSPs
As the "system-on-a-chip" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a varie...
Jan M. Rabaey, Marlene Wan