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CAV
1998
Springer
175views Hardware» more  CAV 1998»
15 years 1 months ago
An ACL2 Proof of Write Invalidate Cache Coherence
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
J. Strother Moore
83
Voted
ICS
1998
Tsinghua U.
15 years 1 months ago
Data Prefetching for Software DSMs
In this paper we propose and evaluate the Adaptive++ technique, a novel runtime-only data prefetching strategy for software-based distributed shared-memory systems (software DSMs)...
Ricardo Bianchini, Raquel Pinto, Claudio Luis de A...
FCCM
1997
IEEE
103views VLSI» more  FCCM 1997»
15 years 1 months ago
An FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
Norman Margolus
VECPAR
1998
Springer
15 years 1 months ago
Simulating Magnetised Plasma with the Versatile Advection Code
Abstract. Matter in the universe mainly consists of plasma. The dynamics of plasmas is controlled by magnetic fields. To simulate the evolution of magnetised plasma, we solve the e...
Rony Keppens, Gábor Tóth
VLDB
1998
ACM
147views Database» more  VLDB 1998»
15 years 1 months ago
Architecture of Oracle Parallel Server
Oracle Parallel Server (OPS) is a shared disk RDBMS. We present a high level overview of the main architectural issues of OPS and their evolution throughout the releases of the Or...
Roger Bamford, D. Butler, Boris Klots, N. MacNaugh...