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RECONFIG
2008
IEEE
268views VLSI» more  RECONFIG 2008»
15 years 6 months ago
Parametric, Secure and Compact Implementation of RSA on FPGA
1 We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The desig...
Ersin Oksuzoglu, Erkay Savas
MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
15 years 6 months ago
A novel cache architecture with enhanced performance and security
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
Zhenghong Wang, Ruby B. Lee
ARC
2009
Springer
241views Hardware» more  ARC 2009»
15 years 6 months ago
Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm
As the need for information security increases in our everyday life, the job of encoding/decoding for secure information delivery becomes a critical issue in data network systems. ...
Jaeyoung Yi, Karam Park, Joonseok Park, Won Woo Ro
JDCTA
2010
175views more  JDCTA 2010»
14 years 6 months ago
Evolution Cipher against Differential Power Attack
: Differntial Power Attack (DPA) is one kind of Side Channel Attacks (SCAs). There are two phases in DPA attacks: sample collection and statistical analysis, which can be utilized ...
Shubo Liu, Ming Tang, Si Gao, Huanguo Zhang