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» Sign bit reduction encoding for low power applications
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75
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KES
2005
Springer
15 years 3 months ago
Reconfigurable Power-Aware Scalable Booth Multiplier
Abstract. An energy-efficient power-aware design is highly desirable for digital signal processing functions that encounter a wide diversity of operating scenarios in battery-power...
Hanho Lee
ISLPED
2000
ACM
91views Hardware» more  ISLPED 2000»
15 years 2 months ago
New clock-gating techniques for low-power flip-flops
Two novel low power flip-flops are presented in the paper. Proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. Presented cir...
Antonio G. M. Strollo, E. Napoli, Davide De Caro
ISLPED
2005
ACM
100views Hardware» more  ISLPED 2005»
15 years 3 months ago
A tunable bus encoder for off-chip data buses
Off-Chip buses constitute a significant portion of the total system power in embedded systems. Past research has focused on encoding contiguous bit positions in data values to red...
Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Wa...
SODA
2008
ACM
144views Algorithms» more  SODA 2008»
14 years 11 months ago
Fast dimension reduction using Rademacher series on dual BCH codes
The Fast Johnson-Lindenstrauss Transform (FJLT) was recently discovered by Ailon and Chazelle as a novel technique for performing fast dimension reduction with small distortion fr...
Nir Ailon, Edo Liberty
91
Voted
TSP
2008
149views more  TSP 2008»
14 years 9 months ago
Decentralized Quantized Kalman Filtering With Scalable Communication Cost
Estimation and tracking of generally nonstationary Markov processes is of paramount importance for applications such as localization and navigation. In this context, ad hoc wireles...
Eric J. Msechu, Stergios I. Roumeliotis, Alejandro...