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SIPS
2007
IEEE
16 years 1 months ago
An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding
Stochastic decoding is a new alternative method for low complexity decoding of error-correcting codes. This paper presents the first hardware architecture for stochastic decoding...
Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gros...
VTC
2007
IEEE
152views Communications» more  VTC 2007»
16 years 1 months ago
Iterative (TURBO) IQ Imbalance Estimation and Correction in BICM-ID for Flat Fading Channels
—TURBO principle has been exploited gainfully to implement many receiver functions. RF front-end impairments are a serious issue in high spectral efficient applications. IQ imba...
Raghunath Cherukuri, Poras T. Balsara
ESTIMEDIA
2007
Springer
16 years 1 months ago
Data-Parallel Code Generation from Synchronous Dataflow Specification of Multimedia Applications
Embedded software design for MPSoC needs parallel programming. Popular programming languages such as C and C++ are not adequate for initial specification since they are designed f...
Seongnam Kwon, Choonseung Lee, Soonhoi Ha
APCCAS
2006
IEEE
245views Hardware» more  APCCAS 2006»
16 years 1 months ago
Digital Audio Broadcasting System Modeling and Hardware Implementation
— DAB is a growing communication technology for digital audio broadcasting and demands higher concentration on flexible and cost optimum implementations for use in new mobile ele...
Nariman Moezzi Madani, Hamed Holisaz, Seid Mehdi F...
ASAP
2006
IEEE
110views Hardware» more  ASAP 2006»
16 years 1 months ago
Loop Transformation Methodologies for Array-Oriented Memory Management
Abstract – The storage requirements in data-dominant signal processing systems, whose behavior is described by arraybased, loop-organized algorithmic specifications, have an imp...
Florin Balasa, Per Gunnar Kjeldsberg, Martin Palko...