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ICCAD
1997
IEEE
94views Hardware» more  ICCAD 1997»
15 years 11 months ago
High-level scheduling model and control synthesis for a broad range of design applications
This paper presents a versatile scheduling model and an efficient control synthesis methodology which enables architectural (high-level) design/synthesis systems to seamlessly su...
Chih-Tung Chen, Kayhan Küçük&cced...
175
Voted
DAC
1997
ACM
15 years 11 months ago
Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets
The paper presents an algorithm to determine the close-tosmallest possible data buffer sizes for arbitrary synchronous data flow (SDF) applications, such that we can guarantee the...
Marleen Adé, Rudy Lauwereins, J. A. Peperst...
206
Voted
ISSS
1996
IEEE
134views Hardware» more  ISSS 1996»
15 years 11 months ago
ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures
An address generation and optimization environment (ADOPT) for distributed memory architectures, is presented. ADOPT is oriented to minimize the area overhead introduced by the us...
Miguel Miranda, Francky Catthoor, Martin Janssen, ...
191
Voted
CHI
1996
ACM
15 years 11 months ago
NewsComm: A Hand-Held Interface for Interactive Access to Structured Audio
The NewsComm system delivers personalized news and other program material as audio to mobile users through a hand-held playback device. This paper focuses on the iterative design ...
Deb K. Roy, Chris Schmandt
187
Voted
ICCAD
1994
IEEE
110views Hardware» more  ICCAD 1994»
15 years 11 months ago
Test pattern generation based on arithmetic operations
Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces signi cant area overhead and performance degradation...
Sanjay Gupta, Janusz Rajski, Jerzy Tyszer