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» Signal integrity management in an SoC physical design flow
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ASPDAC
2006
ACM
148views Hardware» more  ASPDAC 2006»
14 years 6 days ago
An automated design flow for 3D microarchitecture evaluation
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...
Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Re...
TECS
2008
119views more  TECS 2008»
13 years 6 months ago
Fast exploration of bus-based communication architectures at the CCATB abstraction
straction SUDEEP PASRICHA and NIKIL DUTT University of California, Irvine and MOHAMED BEN-ROMDHANE Newport Media Inc. Currently, system-on-chip (SoC) designs are becoming increasin...
Sudeep Pasricha, Nikil Dutt, Mohamed Ben-Romdhane
GLVLSI
2003
IEEE
122views VLSI» more  GLVLSI 2003»
13 years 11 months ago
Cooling of integrated circuits using droplet-based microfluidics
Decreasing feature sizes and increasing package densities are making thermal issues extremely important in IC design. Uneven thermal maps and hot spots in ICs cause physical stres...
Vamsee K. Pamula, Krishnendu Chakrabarty
DATE
2003
IEEE
115views Hardware» more  DATE 2003»
13 years 11 months ago
Embedded Software in Digital AM-FM Chipset
The new standard DRM for digital radio broadcast in AM band requires integrated devices for radio receivers at low cost and very low power consumption. A chipset is currently desi...
Michel Sarlotte, Bernard Candaele, J. Quevremont, ...
ICCAD
2006
IEEE
99views Hardware» more  ICCAD 2006»
14 years 3 months ago
Information theoretic approach to address delay and reliability in long on-chip interconnects
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra