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127
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ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
15 years 8 months ago
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays
Microprocessor clock frequency has improved by nearly 40% annually over the past decade. This improvement has been provided, in equal measure, by smaller technologies and deeper p...
M. S. Hrishikesh, Doug Burger, Stephen W. Keckler,...
DAWAK
2000
Springer
15 years 8 months ago
Applying Vertical Fragmentation Techniques in Logical Design of Multidimensional Databases
In the context of multidimensional databases implemented on relational DBMSs through star schemes, the most effective technique to enhance performances consists of materializing re...
Matteo Golfarelli, Dario Maio, Stefano Rizzi
AGP
1995
IEEE
15 years 7 months ago
Constraint Systems for Pattern Analysis of Constraint Logic-Based Languages
Pattern analysis consists in determining the shape of the set of solutions of the constraint store at some program points. Our basic claim is that pattern analyses can all be desc...
Roberto Bagnara
ASPDAC
2005
ACM
81views Hardware» more  ASPDAC 2005»
15 years 5 months ago
Design and design automation of rectification logic for engineering change
In a later stage of a VLSI design, it is quite often to modify a design implementation to accommodate the new specification, design errors, or to meet design constraints. In addit...
Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang...
116
Voted
ENGL
2008
100views more  ENGL 2008»
15 years 3 months ago
HIDE+: A Logic Based Hardware Development Environment
With the advent of System-On-Chip (SOC) technology, there is a pressing need to enhance the quality of ools available and increase the level of abstraction at which hardware is des...
Abdsamad Benkrid, Khaled Benkrid