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JCP
2007
181views more  JCP 2007»
14 years 11 months ago
Reducing Energy Consumption of Wireless Sensor Networks through Processor Optimizations
When the environmental conditions are stable, a typical Wireless Sensor Network (WSN) application may sense and process very similar or constant data values for long durations. Thi...
Gürhan Küçük, Can Basaran
WMPI
2004
ACM
15 years 5 months ago
A compressed memory hierarchy using an indirect index cache
Abstract. The large and growing impact of memory hierarchies on overall system performance compels designers to investigate innovative techniques to improve memory-system efficienc...
Erik G. Hallnor, Steven K. Reinhardt
ICPP
1994
IEEE
15 years 4 months ago
A Distributed Cache Coherence Protocol for Hypercube Multiprocessors
- This paper proposes a distributed directory cache coherence protocol and compares the performance of the proposed protocol with fully mapped and single linked list protocols for ...
Yeimkuan Chang, Laxmi N. Bhuyan, Akhilesh Kumar
ISCA
1993
IEEE
153views Hardware» more  ISCA 1993»
15 years 4 months ago
An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing
Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a writeinvalidate protocol result in invalidation actions that could be elimin...
Per Stenström, Mats Brorsson, Lars Sandberg
ICDCS
2010
IEEE
15 years 3 months ago
A New Buffer Cache Design Exploiting Both Temporal and Content Localities
: This paper presents a Least Popularly Used buffer cache algorithm to exploit both temporal locality and content locality of I/O requests. Popular data blocks are selected as refe...
Jin Ren, Qing Yang